Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for over twenty years for interconnecting high I/O(input/output) count and area array solder bumps on the silicon chips to the base rigid ceramic chip carriers, for example alumina carriers. The solder bump, typically a 95 Pb/5 Sn alloy, provides the means of chip attachment to the rigid ceramic chip carrier for subsequent usage and testing. For example, see U.S. Pat. Nos. 3,401,126 and 3,429,040 to Miller and assigned to the assignee of the present application, for a further discussion of the controlled collapse chip connection (C4) technique of face down bonding of semiconductor chips to a rigid ceramic carrier. Typically, a malleable pad of metallic solder is formed on the semiconductor device contact site and solder joinable sites are formed on the conductors on the rigid chip carrier.
The device carrier solder joinable sites are surrounded by non-solderable barriers so that when the solder on the semiconductor device contact sites melts, surface tension of the molten solder prevents collapse of the joints and thus holds the semiconductor device suspended above the rigid carrier.
Usually the integrated circuit semiconductor devices are mounted on rigid supporting substrates made of materials with coefficients of expansion that differ from the coefficient of expansion of the material of the semiconductor device, i.e. silicon. Normally the device is formed of monocrystalline silicon with a coefficient of expansion of 2.5.times.10.sup.-6 per .degree.C. and the substrate is formed of a ceramic material, typically alumina with a coefficient of expansion of 5.8.times.10.sup.-6 per .degree.C. In operation, the active and passive elements of the integrated semiconductor device inevitably generate heat resulting in temperature fluctuations in both the devices and the supporting substrate since the heat is conducted through the solder bonds. The devices and the substrate thus expand and contract in different amounts with temperature fluctuations, due to the different coefficients of expansion. This imposes stresses on the relatively rigid solder terminals.
The stress on the solder bonds during operation is directly proportional to (1) the magnitude of the temperature fluctuations, (2) the distance of an individual bond from the neutral or central point (DNP), and (3) the difference in the coefficients of expansion of the material of the semiconductor device and the substrate, and inversely proportional to the height of the solder bond, that is the spacing between the device and the support substrate. The seriousness of the situation is further compounded by the fact that as the solder terminals become smaller in diameter in order to accommodate the need for greater density, the overall height decreases.
More recently, an improved solder interconnection structure with increased fatigue life has been disclosed in U.S. Pat. No. 4,604,644 to Beckham, et al. and assigned to the assignee of the present application, disclosure of which is incorporated herein by reference. In particular, U.S. Pat. No. 4,604,644 discloses a structure for electrically joining a semiconductor device to a support substrate that has a plurality of solder connections where each solder connection is joined to a solder wettable pad on the device and a corresponding solder wettable pad on the rigid support substrate, dielectric organic material disposed between the peripheral area of the device and the facing area of the substrate, which material surrounds at least one outer row and column of solder connections but leaves the solder connections in the central area of the device free of dielectric organic material.
The preferred material disclosed in U.S. Pat. No. 4,604,644 is obtained form a polyimide resin available commercially and sold under the trademark AI-10 by Amoco Corporation. AI-10 is formed by reacting a diamine such as p,p'diaminodiphenylmethane with trimellitic anhydride or acylchloride of trimellitic anhydride. The polymer is further reacted with gamma-amino propyl triethoxy silane (A1100) or .beta.-(3,4-epoxy cyclohexyl) ethyltrimethoxy silane (A-186). The coating material is described in IBM TDB Sept. 1970 P. 825.
The dielectric material is typically applied by first mixing it with a suitable solvent and then dispensing it along the periphery of the device where it can be drawn in between the device and substrate by capillary action.
Although the above techniques have been quite successful for attachments to rigid ceramic substrates, the attachment of a semiconductor device to inorganic substrate employing a C4 type connection are not suggested in the prior art. This is probably due to the fact that organic substrates present significant additional problems not experienced with employing rigid ceramic substrates. For example, the differences in the coefficients of thermal expansion of the material of the semiconductor device, i.e. silicon and organic substrates greatly exceed that experienced with ceramic substrates. In fact, coefficient of thermal expansion mismatch is so great that attempts to attach the device to an organic substrate result in destroying any solder bond. Also, due to the flexible nature of organic substrates, including those that are fiber reinforced, the substrates tend to warp or bend during processing and temperature fluctuations. This greatly magnifies the problems associated with the destructive stress forces that would be placed upon any solder joint between the substrate and semiconductor device.
Moreover, organic substrates generally cannot tolerate processing temperatures of the magnitude that can be tolerated by ceramics. However, it would be desirable to be able to directly bond semiconductor chips to an organic substrate such as a printed circuit board by employing solder bumps, and to permit larger DNP chips to be attached to said substrates while still achieving good C4 fatigue life properties.
With contemplated designs it will be difficult to create an exact balance of CTE's and exact layer symmetry to prevent bending. Although these designs will indeed be expected to be reasonably mechanically compatible, we will want to have the most optimum conditions with the lowest stress on the "C4"s. This would provide design versatility for use with a variety of chip sizes, some of which will become very large, for example, the order of 1 inch square.
It also would enable chips to be attached directly on the surface board thereby eliminating an intermediate chip carrier.
Very limited success has been achieved by including copper/Invar/copper in the interior of organic substrate board to bring the coefficient of thermal expansion closer to that of the chip. However, resistance to thermal cycling of such, although somewhat improved, is not especially satisfactory.